So you’ve created aPCB schematicusing OrCAD Capture, and you’re ready to take your design to the next step in the electronic design automation (EDA) process with a PCB layout tool. How would you do it?
好吧，如果你喜欢大多数PCB设计师，那么很高，你抬起头来快速2分钟教程视频，生成必需的“网表”并将其集成到您选择的PCB布局工具中，并直接移动到设计。
But if you’re curious as to what exactly a netlist is, and what’s going on behind the scenes when you create that intermediary file, this post is for you.
What is a netlist?
看看你的原理图，思考一会儿。如果您不得不手动将最重要的信息从原理图中传输到更全面的PCB布局工具中，那么最有效的方法是什么？
You might strip out all the visual elements of a schematic, and just focus on transferring the connections between components. If a net is a connection between two components, a netlist is simply a list of the electrical connections that describe a circuit.
网展者可以在格式方面和他们传达的信息量方面的广泛变化。这是将包含在网列表中的信息类型的示例：
参考指示符（例如电容器的第一个例子C1）
Pin numbers
Signal keywords (e.g. GND)
以下是在Pads-PCB格式中捕获的orcad捕获的网表的简单示例：
*信号* net1
U2.7 C2.2 U3.3 C1.2 U1.5
即使您以前从未遇到过特殊的格式，那么NetLists也非常简单。在上面的Net1中，我们可以看出C2.2指的是电容器的第二实例的引脚2，其电连接到给定通用指定器U2的部分的销7。
There will be a parts list preceding the netlist telling you what each designator is referring to, in this case, U2 refers to a dual in-line package.
文件网表更改
Understanding how to read a netlist will help you troubleshoot errors that occur from using netlists from third-party libraries. Common reasons to modify a netlist include:
Special characters
PIN码更改
Redundant net names
It is important to document any changes you make to a netlist. If you encounter an error during integration, it’s worth checking whether there are any special character violations, pin number mismatches, or redundant net names that need to be addressed before you can start designing your layout.
Another way to avoid netlist violations is to stick to the sameEDA软件ecosystem. OrCAD Capture integrates seamlessly with both OrCAD PCB Editor and the more comprehensive Cadence Allegro PCB layout tool. Check outCadence的PCB设计和分析工具套件today.
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